A list of documents referred in this specification is as follows. The documents shall be referred according to a document number. Document 1: IEEE International Solid-state Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 122-123, 2001, Document 2: U.S. Pat. No. 5,883,827, Document 3: IEEE International Electron Devices meeting, TECHNICAL DIGEST, pp. 803-806, 2001, Document 3: U.S. Pat. No. 6,314,014
Document 1 discloses a sensitive sensing circuit of a magnetoresistive random access memory (MRAM). MRAM stores information utilizing magnetoresistive effect, however, sensitive reading (sensing) operation is demanded to discriminate a minute read-out signal component according to the magnetoresistive ratio of a few tens %.
Document 2 discloses a phase change memory to which stored information is written because a crystal state of a memory cell varies according to Joule heat by current flowing in the memory cell itself. As a recording layer is once melt at temperature exceeding 600° C. by Joule heat when it is turned amorphous, there is a problem that writing current is large, however, the phase change memory has a merit that a value of resistance varies by two digits or three digits according to a crystal state. Therefore, a reading signal is large and sensing operation is easy. Therefore, the phase change memory may realize a highly integrated and high-speed readable nonvolatile memory.
Document 3 discloses the matrix structure of a so-called phase change memory. In FIG. 2B, configuration that a memory cell located at an intersection of a predetermined word line and a predetermined column line (data line) is selected using the word line and plural QREADs selected by a column selection signal is disclosed.
FIG. 2 schematically shows the configuration of the phase change memory shown in FIG. 12 in the document 2. That is, the phase change memory is composed of a memory array, a row decoder XDEC, a column decoder YDEC, a reading circuit RC and a writing circuit WC. In the memory array, a memory cell MCpr is arranged at each intersection of a word line WLp (p=1, - - - , n) and a data line DLr (r=1, - - - , m). In each memory cell, a storage element RM and a selection transistor QM respectively connected in series are inserted between the data line DL and ground. The word line WL is connected to the gate of the selection transistor and a column selection line YSr (r=1, - - - , m) is connected to the corresponding column selection switch QAr.
According to such configuration, when the selection transistor on the word line selected by the row decoder XDEC conducts and further, the column selection switch corresponding to the column selection line selected by the column decoder YDEC conducts, a current path is created in a selected memory cell and a read-out signal is generated on a common data line I/O. As a value of resistance in the selected memory cell is different depending upon stored information, voltage output to the common data line I/O is different depending upon the stored information. Information stored in the selected memory cell is read by discriminating the difference in the reading circuit RC.
As a mobile equipment market recently develops, the demand of a non-volatile memory represented by a ferroelectric random access memory (FeRAM) and a flash memory increases. However, these memories have such problems in reliability, operational speed, power consumption and a degree of integration that a read/write frequency is limited. Therefore, for a high-speed and low-power non-volatile memory, the above-mentioned magnetoresistive random access memory (MRAM) utilizing magnetoresistive effect and the above-mentioned phase change memory attract attention.
These inventors discussed a signal sensing method of MRAM and the phase change memory prior to this application. As a result, they found that the following were not considered in the memory array configuration shown in FIG. 2. As selection transistors in all memory cells connected to a selected word line conduct during operation, a current path is also created in unselected cells in case the potential of an unselected data line is not ground potential. Therefore, multiple unselected data lines may be charged or discharged and power consumption may increase. Besides, an adjacent data line interferes with a read-out signal that emerges on the selected data line because of capacity coupling noise between data lines and stable read-out operation may be difficult. As an equivalent circuit in read-out operation in a memory cell of MRAM is the same as the phase change memory shown in FIG. 2, the above-mentioned problems are common in MRAM.
The object of the invention is to solve these problems. That is, the object of the invention is to avoid the problems caused by the conduction of transistors in all memory cells on a selected word line.